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Die kleinsten Nodes erhalten mehr Aufmerksamkeit von MRAM

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    Magneto-resistive RAM (MRAM) appears to be gaining traction at the most advanced nodes, in part because of recent improvements in the memory itself and in part because new markets require solutions for which MRAM may be uniquely qualified.

    There are still plenty of skeptics when it comes to MRAM, and lots of potential competitors. That has limited MRAM to a niche role over the past couple decades, hampered by high costs, low density, and lower endurance. But the number of proponents is growing.

    Fig. 1: Standalone memory annual shipments in petabytes, 2022-2033. Source: Objective Analysis/Coughlin Associates, 2023

    Fig. 1: Standalone memory annual shipments in petabytes, 2022-2033. Source: Objective Analysis/Coughlin Associates, 2023

    Today there are two major types of MRAM, standalone and embedded, and three primary application areas:

    • Non-volatile RAM (NVRAM), which is where eMRAM competes with embedded SRAM and embedded DRAM;
    • eMRAM, which can be designed in at the most advanced nodes to compete with flash, and
    • Frame-buffer MRAM, which typically is aimed at displays.

    “Frame buffer-type MRAM is used in photography or video and tuned for endurance and speed,” said Martin Keim, senior engineering director for Tessent at Siemens EDA. “The tradeoff is that the volatility is just down to a few seconds. But if you’re just capturing a picture, it needs to be stored for a second inside of the silicon, and then it will be moved to permanent storage. Ultimately, the advantages of different MRAMs really comes down to what you want to build.”

    Foundries offer different variants of MRAM, each with different PPA metrics. “There is a need in the market space for different eMRAM variants that provide certain PPA metrics,” said Bhavana Chaurasia, product manager at Synopsys. “For example, one could be more SRAM-like, which would be higher speed and smaller in area, but with a lower retention period, versus non-volatile eMRAM, which would have a higher retention period with a slower speed and a bit bigger area. So now you have flexibility, based on the application and target market, you can decide which type of eMRAM to use for your SoC.”

    MRAM isn’t a slam dunk at leading-edge nodes, and it certainly won’t replace DRAM, which was an initial goal. “Several emerging memory technologies have advanced to the point where they have been qualified for production in densities between Mb and Gb,” explained Gary Bronner, senior vice president at Rambus Labs. “These include phase-change memory, such as PCM or 3D Xpoint, MRAM, and ReRAM. To replace DRAM, however, these memories would need to have similar performance to DRAM at an improved cost. None of the emerging memories has yet been able to demonstrate the needed cost and performance to displace DRAM. MRAM and ReRAM are finding homes as replacements for embedded flash, with MRAM being the higher-performance, higher-cost option, and ReRAM being the cost-effective alternative.”

    Still, MRAM’s footprint appears to be widening. Newer developments have helped overcome its historical limitations. At the same time, flash is limited at leading-edge nodes, and MRAM is particularly well suited to automotive applications.

    “MRAM came into importance for the microelectronic industry because there was a lack of solutions to replace flash memories at advanced logic nodes,” said Sebastien Couet, program director magnetics at imec. “STT MRAM has basically been in production for the last two to three years in most major foundries. This is an important first step, because it’s very rare to introduce new memory technology in the industry. SRAM, DRAM, and flash have evolved a lot in the last 50 years, but fundamentally, they’re the same technologies. That we reached high-volume manufacturing capabilities [for MRAM] is a really important milestone. It’s expected to grow drastically in the next 5 to 10 years.”

    MRAM applications
    As a magnetic technology, MRAM is inherently rad-hard. That makes the standalone version popular for aerospace applications, which also are less price-sensitive. “It’s relatively big, and in the memory world, size means cost,” Couet said. “It’s good for spacecraft, which can afford to spend €5,000 on a few megabytes of memory, but obviously it’s not good for consumer markets.”

    MRAM also has found a home in enterprise storage, like IBM’s flash core module (Fig. 3, Col. 1), where Everspin’s MRAM is used as a buffer in case of accidental power loss.

    In addition, MRAM is used in industrial applications, noted Jim Handy, principal analyst with Objective Analysis. As an example, he cited how it keeps carefully choreographed industrial robots from clobbering each other when they restart after a power failure by retaining correct arm positions.

    “Some of these applications need to have a very fast write capability, and need to be non-volatile,” Handy explained. “The big-volume non-volatile memories today are NAND flash, NOR flash, and EEPROM, which is a really small market. All three have extraordinarily slow write speeds and consume a lot of energy, which makes them unpopular for certain applications that need to store data quickly. The alternative is SRAM, with a battery to back it up, but that’s unpopular because the batteries need to get replaced every couple of years.”

    eMRAM in automotive
    But it’s automotive that really has tilted the balance, shifting from flash to eMRAM because of the increasing demands for MCUs bumping up against the increasing costs of creating flash, which could require a dozen or so mask adders.

    “Below the 32nm node, the cost of co-integrating flash memory together with the CPU was skyrocketing because the way to fabricate it was diverging from the logic,” imec’s Couvet said. “You needed to have specific steps in the fab for only making flash. At some point, it really became crazy that the flash fabrication costs more than the rest, so the industry was looking for a solution.”

    The solution turned out to be eMRAM. In 2022, Renesas addressed the issue within its announcement of an STT-MRAM test chip at the 2002 VLSI Symposium, “MRAM fabricated in BEOL is advantageous compared to flash memory fabricated in FEOL for sub-22 nm processes because it is compatible with existing CMOS logic process technology and requires fewer additional mask layers,” the company said at the time.

    IBM is even more bullish. “In about three years, you’ll be able to point to every new car on the street and say there is eMRAM inside that car,” said Daniel Worledge, distinguished research staff member and senior manager at IBM. “There is no more embedded flash in advanced nodes, all the foundries have stopped developing it. The transition period was 22nm and 28nm, depending on the foundry.”

    Embedded MRAM also is inherently scalable. “eFlash is reaching its limit to scale below 28nm, while with eMRAM you can design embedded non-volatile memories supporting lower technology nodes,” Chaurasia said. “The benefit is achieving scalability in core as well as memory. Memory can remain part of the same die, which helps achieve a smaller area and better performance and power compared to the other option, to keep memory in a separate die, which leads to performance and power loss in the interface and increases security concerns. eMRAM offers a smaller area, lower leakage, higher capacity, and better radiation immunity. Compared to PCRAM and ReRAM, eMRAM has lower temperature sensitivity, provides better production-level yields, and offers longer endurance (retaining data over multiple read/write cycles over many years). It allows word-level erase and program operation, making it a power-efficient NVM solution. All these benefits make eMRAM an excellent eNVM.”

    All of these benefits could make eMRAM the future of automotive memory, at least according to its proponents. Not everyone agrees, however.

    “When we talk to automotive customers, they prefer ReRAMs over MRAMs,” Keim said. “The arguments we hear are temperature stability and concern about magnetic fields in the automotive environment impacting the data stored in the MRAM. For the former, there are now MRAM types that do have the temperature stability required for the automotive market (-40C to +150C). This underlines that MRAM technology is rapidly expanding into all corners of the application space. It is a different question how far their productization has developed so that an automotive user may select those, readily available in the market.”

    On the other hand, MRAMs have a very narrow gap between legal read values for 0 and 1 (see the trimming discussion below). This small gap narrows and shifts with increasing temperature, making it more difficult to safely interpret the read values. The resistance gap between 0 and 1 is much wider in ReRAMs, making it easier to read, i.e., easier to operate at higher temperatures.

    Even so, this May NXP and TSMC announced the first 16nm finFET eMRAM for automotive, which can update 20MB of code in approximately 3 seconds compared to flash’s 1 minute, offering up to 1 million update cycles, and a level of endurance 10X greater than flash and other emerging memory technologies.

    The competition among old and new memory types isn’t just technical and financial. Imagine if an ambulance had to pause a full minute before it could start.

    Technological advances
    Like so many devices in the technology industry, MRAM began with Nobel-prize winning work. In this case, it was the discovery of giant magnetoresistance, the concept underlying hard disk storage. The next breakthrough was spin-transfer torque (STT), an effect in which the orientation of a magnetic layer in a magnetic tunnel junction (MTJ) or spin valve can be modified using a spin-polarized current.

    This new physics led to more effective MRAMs. The MTJ at the heart of STT MRAMs is made of two magnetic electrodes and one dielectric tunnel barrier in between. “Basically, the MJT is responsible for the detection of the magnetic state of one of the two electrodes,” Couet explained. “In MRAM you have a fixed magnet, then the tunnel barrier, and then a free magnet that you can program to be either pointing up or pointing down, for example. Then you compare. After that, the resistance of the junction depends on the alignment of the electrodes. If both electrodes are aligned in the parallel configuration in terms of their magnetic states, then they have a low resistance. If they’re anti-parallel, they have a high resistance. That gives a means to distinguish between magnets pointing up and pointing down, so you can store information that way. The magnets can be stable over a long time, as is known from hard drives.”

    STT MRAM currently predominates. An earlier form, field-switched MRAM (now known as toggle MRAM), was first brought to market in 2006 by Motorola’s Freescale, which was spun off and incorporated as Everspin Technologies. Everspin provides most of the standalone MRAM in today’s market in both toggle and STT forms.

    “In toggle MRAM, the polarity is changed by applying a magnetic field across the MTJ,” explained Joe O’Hare, senior director of marketing at Everspin. “By contrast, STT MRAM technology uses the spin-transfer torque property, or the manipulation of the spin of electrons with a polarizing current.”

    Fig. 2: Toggle field-switched and spin-transfer torque magnetic tunnel junction operation. Source: Everspin

    Fig. 2: Toggle field-switched and spin-transfer torque magnetic tunnel junction operation. Source: Everspin

    In 2010, Worledge and his IBM colleagues, and the Ohno lab at Tohoku University in Japan, both published papers showing perpendicular STT MRAM, which inspired the current interest. “Before then, MRAM was kind of a laboratory curiosity,” said Worledge. “You could make some bits but they didn’t switch reliably. The reason was all the magnetization was in-plane, but that’s very inefficient. What you want is to have magnetization perpendicular to the plane of the wafer.”

    Although the answer had been known theoretically since 1996, it would take over a decade to craft the right combination of physics and materials to achieve optimal switching. “Perpendicular bits solve the write problem,” Worledge explained. “And that’s what kicked off all of this excitement. All the big companies jumped in and started to work on STT RAM.”

    There’s also a new variation called spin-orbit torque (SOT)-MRAM, which imec has been refining. As Couet explained in a blog, “The main difference between STT- and SOT-MRAM resides in the current injection geometry used for the write process. While in STT-MRAM, the current is injected perpendicularly into the MTJ, current injection in SOT-MRAM happens in-plane, in an adjacent SOT layer.”

    Learning Curve
    Still, the complicated physics means there are complexities to working with MRAMs that designers need to be aware of.

    “When you buy a SRAM or DRAM off the market, they’re all more or less the same,” Keim said. “With the MRAMs, with all the different underlying physics and properties, you can run into trouble if you choose the wrong one.”

    MRAMs have probabilistic behaviors, so they also come with a lot of error correction. “Normally, you have an ECC that has maybe one bit of error correction and two bits of error detection. MRAM is one level up, at least two-bit correction and three-bit detection,” Keim said. “And then, the ECC is going to correct the improbability of the MRAM. So together, you gain the behavior of a deterministic, just like an SRAM, but it costs you.”

    There’s an additional issue, as well. “When you turn on an SRAM and you’re writing and reading, it just works. With MRAM, you first have to train your reading and writing circuitry on the actual properties of the cell, in what’s called ‘trimming,’ he said. “Trimming means you have to find your comparison value, your resistive value, that makes you decide if what you have just read should be interpreted as a 0 or a 1. So there is an entire cycle of trim learning that the MRAM needs for both reads and writes.”

    It doesn’t end there. “Different sections of the memory need different trim values. There is a whole process involved to get that thing actually working,” he said. “Once you have accomplished that, you have your beefed up ECC, you have done your trim circuitry, which needs to be on-chip. It’s too much data to be done off-chip, it would be too time-consuming and expensive. So you have to invest additional hardware just for that trim learning. The only viable solution is to do all of this on-chip, fully automated and self-contained. To further reduce the area costs, you want to take advantage of the DFT you already have, namely a memory built-in self-test (MBiST) engine.”

    The good news is that after all that additional time and money have been invested, the memory works quite well.

    MRAM’s thermal advantages
    Thermal is DRAM’s weak point. Higher temperatures cause its capacitors to refresh and lose data. “DRAM is a difficult technology to use. It forgets things in milliseconds and needs to go offline periodically to refresh,” said Marc Greenberg, group director, product marketing at Cadence. “It’s susceptible to heat and radiation.”

    By contrast, one of the important reasons for eMRAM’s success is that it stays stable at high temperatures — so much so that it can retain data through solder reflow. However, its thermal advantage also explains its relative lack of endurance.

    “Because you need to have really good data retention in order to withstand solder reflow, you have to make the magnetic bit really difficult to switch, because you don’t want it to switch during thermal fluctuations,” IBM’s Worledge said. “That means it’s also difficult to switch when you write it, so you have to apply a larger voltage to write it. That larger voltage will damage the MgO tunnel barrier over time.”

    MRAM magnetic field disadvantages
    Every technology has its Achilles’s heel. For MRAM, it is strong magnetic fields.

    “Like any magnetic component, eMRAM should maintain a distance from other magnetic components,” said Chaurasia. “For example, there can be inductor coils within an SoC or die. A certain distance between such devices reduces the magnetic effect. Hence, it must be maintained when designing a chip. For off-chip magnetic immunity, advanced packaging can provide shielding. Air gaps above the eMRAM block or the device can also provide immunity from magnetic sensitivity.”   

    Unlike being near MRI machines, which is a definite no-no, IBM’s Worledge said proximity to small motors and small inductor coils should not be an issue. Nevertheless, he did suggest one nightmare scenario — an attacker using a neodymium iron boron magnet potentially could disable eMRAM chips, so it would be best to put such chips at least a centimeter away from the surface of devices, especially cars.

    The future of MRAM
    There are a number of near-term and long-term developments in the works for MRAM. Mobile cache, in which MRAM would replace both flash and SRAM, could be in the market within the next year or two, according to IBM’s Worledge. “From the research and development point of view, I think we’re done. We’ve demonstrated the magnetic tunnel junctions that can meet these requirements, and we’re hoping the foundries will offer a commercial offering soon.”

    Fig. 3: Standalone MRAM and embedded non-volatile MRAM are already in the market. Mobile cache MRAM and last-level cache MRAM are in development. Source: IBM

    Fig. 3: Standalone MRAM and embedded non-volatile MRAM are already in the market. Mobile cache MRAM and last-level cache MRAM are in development. Source: IBM

    Worledge is confident there’s a killer app in eMRAM’s future. “Let’s say you had an IoT device that’s powered by solar power. Maybe it’s part of a security system. It’s normally off, maybe it has a little sensor on it to pick up some audio. When the audio gets loud enough, it wakes up and tries to determine with some AI algorithm whether or not there’s an intruder. Without eMRAM, it would wake up, load the weights for the AI program from flash into SRAM, then run the AI program. If the weights were updated, they’d have to write back to flash, which is incredibly power-intensive. But with eMRAM alone, when the device wakes up, it just starts operating because all the weights are already inside the eMRAM.”

    Such a scheme would be slower than SRAM, but the advantage is lower power compared to writing data back and forth between the flash and SRAM, and its endurance would make it ideal for field operations, he said.

    IBM’s “holy grail,” which the company has been working on for nearly a quarter of a century, is last-level cache. Current cache schemes depend on SRAM for working memory and can have a hiccup called a “cache miss,” in which the data isn’t in SRAM. That forces the SRAM to go all the way out to DRAM to get the data.

    “It’s a very slow, like 35 nanoseconds or 50 nanoseconds round-trip,” said Worledge. “You’d really like to have a bigger SRAM cache if you could. If the MRAM was twice as dense as SRAM, you’d have twice as many bits in there. It would be a little slower than the SRAM, but you more than make up for the slower speed with having twice as many bits.”

    Worledge believes they’re finally within striking distance. “It’s a very challenging application because you need the MRAM to be very dense and very fast and high endurance,” he said. “We still need to lower the switching current. We published on a new device we invented called the double spin torque magnetic tunnel junction that does lower the switching current by a factor of two. We even showed 250-picosecond switching, which is incredibly fast compared to all other MRAM publications. There’s a lot of promise there, but we’re still in research mode on that.”

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